.W 60
.V 10
.CT Holden Rohrer
.V 2
.CT Applications of Engineering: Pd 3
.V 2
.CT Phrase Project
.V 5
.FIL =
.CT Table of Contents

.LD 1| . |Problem Statement
.LD 2| . |Truth Table
.LD 3| . |Unsimplified Boolean Expressions
.LD 4| . |Karnaugh-like Depthy Mapping
.LD 5| . |Berkeley's ABC
.LD 6| . |Simplified Boolean Expressions
.LD 7| . |Difficulties
.LD Appendix A: circ.ps| . |Logic Diagram
.LD Appendix B: schematic.{png,dxf}| . |LibreCAD Schematic

.FIL =
.CT Problem Statement

The objective of this project is to, using 74LS series chips (00, 04, 08, 11, 21, 32) and an anode seven-segment display (FND507) deisplay a 16-letter phrase with varying input switches. Jumper wires, a breadboard, and a "Breadboard Assistant" will be used to connect these components.
    The phrase I will display is "AUTOCADSCHEMATIC," each letter displayed corresponding directly to the following cube vertices/switch positions (so chosen that any two consecutive states only require one switch instead of four like in 0111->1000):
    0000 -> 0001 -> 0011 -> 0010 -> 0110 -> 0111 -> 0101 -> 0100 -> 1100 -> 1101 -> 1111 -> 1110 -> 1010 -> 1011 -> 1001 -> 1000.
    The breadboard will use the following wire colors convention:
- GND = PINK
- PWR = WHITE
- W = DARK YELLOW
- !W = WHITE
- X = DARK RED
- !X = YELLOW
- Y = GREEN
- !Y = RED
- Z = GRAY
- !Z = BLUE
- AND = ORANGE
- OR = PURPLE
- NOT = RED
- NAND = BLUE
    The Seven-Segment Display will use the following light naming convention:
 _______
|   a   |
|       |b
|f      |
|_______|
|    g  |
|e      |c
|       |
|_______|
    d
.FIL =
.CT Truth Table

W X Y Z | VAL | A B C D E F G (1=OFF, 0=ON)
========+=====+==============
0 0 0 0 |  A  | 0 0 0 1 0 0 0
0 0 0 1 |  U  | 1 0 0 0 0 0 1
0 0 1 1 |  T  | 1 1 1 0 0 0 0
0 0 1 0 |  O  | 0 0 0 0 0 0 1
0 1 1 0 |  C  | 0 1 1 0 0 0 1
0 1 1 1 |  A  | 0 0 0 1 0 0 0
0 1 0 1 |  D  | 1 0 0 0 0 1 0
0 1 0 0 |  S  | 0 1 0 0 1 0 0
1 1 0 0 |  C  | 0 1 1 0 0 0 0
1 1 0 1 |  H  | 1 1 0 1 0 0 0
1 1 1 1 |  E  | 0 1 1 0 0 0 0 
1 1 1 0 |  M  | 0 1 0 1 0 1 1
1 0 1 0 |  A  | 0 0 0 1 0 0 0
1 0 1 1 |  T  | 1 1 1 0 0 0 0
1 0 0 1 |  I  | 1 1 1 1 0 0 1
1 0 0 0 |  C  | 0 1 1 0 0 0 0

.FIL =
.CT Unsimplified Boolean Expressions
.LS
    ___    __     _ _      _     _      __
A = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
.ELS
.LS
    __     _  _   _ __     __     _              _    _      __     ___
B = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
.ELS
.LS
    __     _  _     __           _      __     ___
C = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
.ELS
.LS
    ____   _        _       _    _ _    __
D = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
.ELS
.LS
    _ __
E = WXYZ
.ELS
.LS
    _ _       _
F = WXYZ + WXYZ
.ELS
.LS
    ___    __ _   _  _      _    __
G = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
.ELS
.FIL =
.CT Karnaugh-like Depthy Mapping

    Form:
     Y Z  Y!Z  !Y!Z !Y Z 
 W X #    #    #    #
 W!X #    #    #    #
!W!X #    #    #    #
!W X #    #    #    #
    For reference, the "primitives" (dot=0):

W           !W            X           !X
   1 1 1 1      . . . .      1 1 1 1      . . . .
   1 1 1 1      . . . .      . . . .      1 1 1 1 
   . . . .      1 1 1 1      . . . .      1 1 1 1
   . . . .      1 1 1 1      1 1 1 1      . . . .

Y           !Y            Z           !Z
   1 1 . .      . . 1 1      1 . . 1      . 1 1 .
   1 1 . .      . . 1 1      1 . . 1      . 1 1 . 
   1 1 . .      . . 1 1      1 . . 1      . 1 1 .
   1 1 . .      . . 1 1      1 . . 1      . 1 1 .
 
    And the objectives:
A            B            C            D
   . . . 1      1 1 1 1      1 . 1 .      . 1 . 1
   1 . . 1      1 . 1 1      1 . 1 1      . 1 . 1
   1 . . 1      1 . . .      1 . . .      . . 1 .
   . . . 1      . 1 1 .      . 1 . .      1 . . .

E            F            G
   . . . .      . 1 . .      . 1 . .
   . . . .      . . . .      . . . 1
   . . . .      . . . .      . 1 . 1
   . . 1 .      . . . 1      . 1 . .

The objectives were grouped into 1s, 2s, and 4s, to create the following simple boolean expressions (which are irrelevant to the final solution, but still required).
.FIL =
.CT Simplified Boolean Expressions

A = !YZ + !XZ
B = W!Y + WX + WZ + !XYZ
C = WYZ + !XYZ + W!X!Y + W!Y!Z + !WXY!Z
D = WY!Z + W!YZ + !W!X!Y!Z + !WXYZ
E = !WX!Y!Z
F = WXY!Z + !WX!YZ
G = !X!YZ + !WY!Z + XY!Z
.FIL =
.CT Berkeley's ABC!
I used Berkeley's ABC: github.com/berkeley-abc/abc.
.CT Genlib File
GATE inv    2.3 O=!a;       PIN * INV 1 999 0.9 0.3 0.9 0.3
GATE nand   3.5 O=!(a*b);   PIN * INV 1 999 0.9 0.3 0.9 0.3
GATE and2   3.5 O=a*b;      PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE and3   4.7 O=a*b*c;    PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE and4   7   O=a*b*c*d;  PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE or     3.5 O=a+b;      PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE buf    1   O=a;        PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE zero   0   O=CONST0;
GATE one    0   O=CONST1;

.CT PLA file
..i 4
..o 7
..ilb w x y z
..ob a b c d e f g
0000 0001000
0001 1000001
0011 1110000
0010 0000001
0110 0110001
0111 0001000
0101 1000010
0100 0100100
1100 0110000
1101 1101000
1111 0110000
1110 0101011
1010 0001000
1011 1110000
1001 1111001
1000 0110000
..e

On a Bourne shell with abc binary built in current dir:
$ ./abc -c "read circ.pla; read_library gathing.genlib; strash; collapse; strash; rewrite; strash; dc2; map; choice; map; print_gates; write struct.eqn; show -g;"
$ sed -e 's/new_n//g' -e 's/_//g' struct.eqn > struct.eqn.tmp
$ mv struct.eqn{.tmp,} #with some custom cleanup (NAND, moving !x...)

.CT Network Structure from Berkeley's ABC
a = NAND(y,x) * z;
16 = !w * !y;
17 = x * !w;
18 = 17 + 16;
20 = !z * y;
21 = 20 + 18;
23 = z + !x;
b = NAND(23,21);
25 = !16;
26 = z + !y;
27 = 26 + 17;
28 = y * w;
29 = NAND(z,x);
30 = 29 + 28;
c = 25 * 30 * 27;
32 = z * !y;
33 = 32 + 20;
34 = 33 * w;
35 = !z + y;
36 = 18 * 35 * 23;
d  = 36 + 34;
38 = !z * x;
e  = 38 * 16;
40 = 28 * 38;
41 = 32 * 17;
f  = 41 + 40;
43 = !x * w;
44 = 43 + 26;
45 = 35 + x;
g  = NAND(45,44);

Total cost:
- 12 2AND = 3 74LS08
- 4 NAND  = 1 74LS00
- 5 NOT   = 1 74LS04
- 2 3AND  = 1 74LS11
- 12 OR   = 3 74LS32

.FIL =
.CT Difficulties

This project was, by itself, very doable. However, creation of this document was either to be tedious or difficult because of, for example, the centered headings. I used a C program (https://git.hrhr.dev/badroff) to generate that. The remainder of the project is very likely to be correct because the data table appears to be exactly what's desired, and it was trivial to throw that into abc. Learning abc, at first, appeared to be difficult, but throwing some random sequences of optimization commands with the pla and gate formats was fairly easy. Because I use Linux, I perceived the installation and usage of AutoCAD as difficult, but LibreCAD has an intuitive and very usable interface with cross-platform capabilities (including saved file interoperability with AutoCAD through the dxf format).