diff options
| author | Holden Rohrer <hr@hrhr.dev> | 2020-03-25 21:04:07 -0400 |
|---|---|---|
| committer | Holden Rohrer <hr@hrhr.dev> | 2020-03-25 21:04:07 -0400 |
| commit | 72514a7176be97a6fd5e24bf58f817e5506f84de (patch) | |
| tree | b48bc41a269926e8ca307ca4d0c30c87c82f7c9f | |
| parent | 48295225a4c407d852d7ac3cea3e8373d6958fb2 (diff) | |
ABC work on phrase-circuit
| -rw-r--r-- | gathing-eng/phrase-circuit.src | 46 |
1 files changed, 40 insertions, 6 deletions
diff --git a/gathing-eng/phrase-circuit.src b/gathing-eng/phrase-circuit.src index c939e68..6bff50c 100644 --- a/gathing-eng/phrase-circuit.src +++ b/gathing-eng/phrase-circuit.src @@ -27,12 +27,12 @@ 1 . . . . . . . . . . . . . . . . . . . . .Problem Statement 2 . . . . . . . . . . . . . . . . . . . . . . .Truth Table 3 . . . . . . . . . . . . . . . .Unsimplified Boolean Expressions -4 . . . . . . . . . . . . . . . . . Karnaugh-like depthy mapping -5 . . . . . . . . . . . . . . . . Simplified Boolean Expressions -6 . . . . . . . . . . . . . . . . . . . . . . Logic Diagram -7 . . . . . . . . . . . . . . . . . . . . . . Difficulties -8 . . . . . . . . . . . . . . . . .Appendix A: AutoCAD Schematic -9 . . . . . . . . . . . . . . . . Appendix B: Complete Breadboard +4 . . . . . . . . . . . . . . . . . . . . . .Berkeley's ABC +5 . . . . . . . . . . . . . . . . . . . . . . Logic Diagram +6 . . . . . . . . . . . . . . . . . . . . .Breadboard Schema +6 . . . . . . . . . . . . . . . . . . . . . . Difficulties +7 . . . . . . . . . . . . . . . . .Appendix A: AutoCAD Schematic +8 . . . . . . . . . . . . . . . . Appendix B: Complete Breadboard ================================================================================ .CT Problem Statement @@ -194,3 +194,37 @@ Total cost: - 5 NOT = 1 74LS04 - 2 3AND = 1 74LS11 - 12 OR = 3 74LS32 +================================================================================ +.CT Breadboard Schema + +The positions are labeled as follows: each board has a code "1." or "2.", a set +of rows 1-80, and columns A-E,F-J. The following describe wires on a real +breadboard. Power/GND rails are implied because they aren't complex. All chips +are at "left is low" and for 7-seg, A-E=A-E side. + +74LS00 @ 2.20-26 (NAND) +74LS04 @ 1.30-36 (NOT) +74LS08 @ 1.10-16, 1.20-26, 3.10-16 (2AND) +74LS11 @ 2.10-16 (3AND) +74LS32 @ 2.30-36, 3.20-26, 3.30-36 (OR) +FND507 @ 2.55-2.59 (7-seg) + +0.15J = 1.30A (w) +0.16J = 1.32A (x) +0.17J = 1.34A (y) +0.18J = 1.31G (z) +1.32C = 2.20A (x) +1.34C = 2.21A (y) +2.22C = 1.11I (!x+!y) +1.31G = 1.12G (z) +1.13G = 2.58H ( a=z*(!x+!y) ) +1.31A = 1.10D (!w) +1.33A = 1.11A (!y) +0.16I = 1.13A (x) +1.10A = 1.14A (!w) +1.12A = 2.30A (!w * !y) #16 +1.15A = 2.31A (!w * x) #17 +2.32A = 2.33D (!w!y + !wx) #18 + +================================================================================ +.CT Difficulties |