diff options
| -rw-r--r-- | gathing-eng/badroff.c | 50 | ||||
| -rw-r--r-- | gathing-eng/phrase-circuit.src | 180 |
2 files changed, 93 insertions, 137 deletions
diff --git a/gathing-eng/badroff.c b/gathing-eng/badroff.c deleted file mode 100644 index d318d40..0000000 --- a/gathing-eng/badroff.c +++ /dev/null @@ -1,50 +0,0 @@ -#include <stdio.h> -#include <string.h> - -typedef char bool; -#define true 1 -#define false 0 -int main(int argc, char** argv){ - FILE* in; - if (argc >= 2) - in = fopen(argv[1], "r"); - else - in = stdin; - if (in == NULL){ - perror(argv[1]); - return 1; - } - int c; - bool nl = true; - bool cmd = false; - char cmds[81]; - int cmdlen = 0; - while ( (c = fgetc(in)) != EOF){ - if (c == '\n'){ - if (cmd){ - if (! strncmp(cmds,"CT",2)){ - for (int i=0; i<(83-strnlen(cmds,80))/2; i++) - printf(" "); - printf("%s\n",cmds+3); - } else printf("%s\n",cmds); - cmd = false; - cmds[0] = '\0'; - cmdlen = 0; - } - else printf("\n"); - nl = true; - } - else{ - if (c == '.' && nl) - cmd = true; - else if (cmd){ - cmds[cmdlen] = c; - cmds[cmdlen+1] = '\0'; - cmdlen++; - } - else printf("%c",c); - nl = false; - } - } - return 0; -} diff --git a/gathing-eng/phrase-circuit.src b/gathing-eng/phrase-circuit.src index 6bff50c..37e1b60 100644 --- a/gathing-eng/phrase-circuit.src +++ b/gathing-eng/phrase-circuit.src @@ -1,52 +1,31 @@ - - - - - - - - +.W 72 +.V 10 .CT Holden Rohrer - - +.V 2 .CT Applications of Engineering: Pd 3 - - +.V 2 .CT Phrase Project - - - - - - - - -================================================================================ +.V 5 +.FIL = .CT Table of Contents -1 . . . . . . . . . . . . . . . . . . . . .Problem Statement -2 . . . . . . . . . . . . . . . . . . . . . . .Truth Table -3 . . . . . . . . . . . . . . . .Unsimplified Boolean Expressions -4 . . . . . . . . . . . . . . . . . . . . . .Berkeley's ABC -5 . . . . . . . . . . . . . . . . . . . . . . Logic Diagram -6 . . . . . . . . . . . . . . . . . . . . .Breadboard Schema -6 . . . . . . . . . . . . . . . . . . . . . . Difficulties -7 . . . . . . . . . . . . . . . . .Appendix A: AutoCAD Schematic -8 . . . . . . . . . . . . . . . . Appendix B: Complete Breadboard - -================================================================================ +.LD 1| . |Problem Statement +.LD 2| . |Truth Table +.LD 3| . |Unsimplified Boolean Expressions +.LD 4| . |Karnaugh-like Depthy Mapping +.LD 5| . |Berkeley's ABC +.LD 6| . |Simplified Boolean Expressions +.LD 7| . |Logic Diagram +.LD 8| . |Difficulties +.LD 9| . |Appendix A: AutoCAD Schematic +.LD 10| . |Complete Breadboard + +.FIL = .CT Problem Statement -The objective of this project is to, using 74LS series chips (00, 04, 08, 11, -21, 32) and an anode seven-segment display (FND507) deisplay a 16-letter phrase -with varying input switches. Jumper wires, a breadboard, and a "Breadboard -Assistant" will be used to connect these components.t - The phrase I will display is "AUTOCADSCHEMATIC," each letter displayed -corresponding directly to the following cube vertices/switch positions (so -chosen that any two consecutive states only require one switch instead of four -like in 0111->1000): - 0000 -> 0001 -> 0011 -> 0010 -> 0110 -> 0111 -> 0101 -> 0100 -> 1100 -> 1101 --> 1111 -> 1110 -> 1010 -> 1011 -> 1001 -> 1000. +The objective of this project is to, using 74LS series chips (00, 04, 08, 11, 21, 32) and an anode seven-segment display (FND507) deisplay a 16-letter phrase with varying input switches. Jumper wires, a breadboard, and a "Breadboard Assistant" will be used to connect these components. + The phrase I will display is "AUTOCADSCHEMATIC," each letter displayed corresponding directly to the following cube vertices/switch positions (so chosen that any two consecutive states only require one switch instead of four like in 0111->1000): + 0000 -> 0001 -> 0011 -> 0010 -> 0110 -> 0111 -> 0101 -> 0100 -> 1100 -> 1101 -> 1111 -> 1110 -> 1010 -> 1011 -> 1001 -> 1000. The breadboard will use the following wire colors convention: - GND = BROWN - PWR = WHITE @@ -72,7 +51,7 @@ like in 0111->1000): | | |_______| d -================================================================================ +.FIL = .CT Truth Table W X Y Z | VAL | A B C D E F G (1=OFF, 0=ON) @@ -94,24 +73,78 @@ W X Y Z | VAL | A B C D E F G (1=OFF, 0=ON) 1 0 0 1 | I | 1 1 1 1 0 0 1 1 0 0 0 | C | 0 1 1 0 0 0 0 -================================================================================ +.FIL = .CT Unsimplified Boolean Expressions +.LS ___ __ _ _ _ _ __ A = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ +.ELS +.LS __ _ _ _ __ __ _ _ _ __ ___ B = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ +.ELS +.LS __ _ _ __ _ __ ___ C = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ +.ELS +.LS ____ _ _ _ _ _ __ D = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ +.ELS _ __ E = WXYZ _ _ _ F = WXYZ + WXYZ ___ __ _ _ _ _ __ G = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ - -================================================================================ +.FIL = +.CT Karnaugh-like Depthy Mapping + + Form: + Y Z Y!Z !Y!Z !Y Z + W X # # # # + W!X # # # # +!W!X # # # # +!W X # # # # + For reference, the "primitives" (dot=0): + +W !W X !X + 1 1 1 1 . . . . 1 1 1 1 . . . . + 1 1 1 1 . . . . . . . . 1 1 1 1 + . . . . 1 1 1 1 . . . . 1 1 1 1 + . . . . 1 1 1 1 1 1 1 1 . . . . + +Y !Y Z !Z + 1 1 . . . . 1 1 1 . . 1 . 1 1 . + 1 1 . . . . 1 1 1 . . 1 . 1 1 . + 1 1 . . . . 1 1 1 . . 1 . 1 1 . + 1 1 . . . . 1 1 1 . . 1 . 1 1 . + + And the objectives: +A B C D + . . . 1 1 1 1 1 1 . 1 . . 1 . 1 + 1 . . 1 1 . 1 1 1 . 1 1 . 1 . 1 + 1 . . 1 1 . . . 1 . . . . . 1 . + . . . 1 . 1 1 . . 1 . . 1 . . . + +E F G + . . . . . 1 . . . 1 . . + . . . . . . . . . . . 1 + . . . . . . . . . 1 . 1 + . . 1 . . . . 1 . 1 . . + +The objectives were grouped into 1s, 2s, and 4s, to create the following simple boolean expressions (which are irrelevant to the final solution, but still required). +.FIL = +.CT Simplified Boolean Expressions + +A = !YZ + !XZ +B = W!Y + WX + WZ + !XYZ +C = WYZ + !XYZ + W!X!Y + W!Y!Z + !WXY!Z +D = WY!Z + W!YZ + !W!X!Y!Z + !WXYZ +E = !WX!Y!Z +F = WXY!Z + !WX!YZ +G = !X!YZ + !WY!Z + XY!Z +.FIL = .CT Berkeley's ABC! .CT --------------- I used Berkeley's ABC: github.com/berkeley-abc/abc. @@ -127,10 +160,10 @@ GATE zero 0 O=CONST0; GATE one 0 O=CONST1; .CT PLA file -.i 4 -.o 7 -.ilb w x y z -.ob a b c d e f g +..i 4 +..o 7 +..ilb w x y z +..ob a b c d e f g 0000 0001000 0001 1000001 0011 1110000 @@ -147,12 +180,10 @@ GATE one 0 O=CONST1; 1011 1110000 1001 1111001 1000 0110000 -.e +..e On a Bourne shell with abc binary built in current dir: -$ ./abc -c "read circ.pla; read_library gathing.genlib; strash;\ -collapse; strash; rewrite; strash; dc2; map; choice; map; print_gates;\ -write struct.eqn;" +$ ./abc -c "read circ.pla; read_library gathing.genlib; strash; collapse; strash; rewrite; strash; dc2; map; choice; map; print_gates; write struct.eqn; show -g;" $ sed -e 's/new_n//g' -e 's/_//g' struct.eqn > struct.eqn.tmp $ mv struct.eqn{.tmp,} #with some custom cleanup (NAND, moving !x...) @@ -194,37 +225,12 @@ Total cost: - 5 NOT = 1 74LS04 - 2 3AND = 1 74LS11 - 12 OR = 3 74LS32 -================================================================================ -.CT Breadboard Schema - -The positions are labeled as follows: each board has a code "1." or "2.", a set -of rows 1-80, and columns A-E,F-J. The following describe wires on a real -breadboard. Power/GND rails are implied because they aren't complex. All chips -are at "left is low" and for 7-seg, A-E=A-E side. - -74LS00 @ 2.20-26 (NAND) -74LS04 @ 1.30-36 (NOT) -74LS08 @ 1.10-16, 1.20-26, 3.10-16 (2AND) -74LS11 @ 2.10-16 (3AND) -74LS32 @ 2.30-36, 3.20-26, 3.30-36 (OR) -FND507 @ 2.55-2.59 (7-seg) - -0.15J = 1.30A (w) -0.16J = 1.32A (x) -0.17J = 1.34A (y) -0.18J = 1.31G (z) -1.32C = 2.20A (x) -1.34C = 2.21A (y) -2.22C = 1.11I (!x+!y) -1.31G = 1.12G (z) -1.13G = 2.58H ( a=z*(!x+!y) ) -1.31A = 1.10D (!w) -1.33A = 1.11A (!y) -0.16I = 1.13A (x) -1.10A = 1.14A (!w) -1.12A = 2.30A (!w * !y) #16 -1.15A = 2.31A (!w * x) #17 -2.32A = 2.33D (!w!y + !wx) #18 - -================================================================================ + +.FIL = +.CT Logic Diagram + +See attached circ.ps (PostScript) for a logic diagram +.FIL = .CT Difficulties + +This project was, by itself, very doable. However, creation of this document was either to be tedious or difficult because of, for example, the centered headings. I used a C program (https://git.hrhr.dev/badroff) to generate that. The remainder of the project is very likely to be correct because the data table appears to be exactly what's desired, and it was trivial to throw that into abc. Learning abc, at first, appeared to be difficult, but throwing some random sequences of optimization commands with the pla and gate formats was fairly easy. |