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.CT Holden Rohrer
.CT Applications of Engineering: Pd 3
.CT Phrase Project
================================================================================
.CT Table of Contents
1 . . . . . . . . . . . . . . . . . . . . .Problem Statement
2 . . . . . . . . . . . . . . . . . . . . . . .Truth Table
3 . . . . . . . . . . . . . . . .Unsimplified Boolean Expressions
4 . . . . . . . . . . . . . . . . . . . . . .Berkeley's ABC
5 . . . . . . . . . . . . . . . . . . . . . . Logic Diagram
6 . . . . . . . . . . . . . . . . . . . . .Breadboard Schema
6 . . . . . . . . . . . . . . . . . . . . . . Difficulties
7 . . . . . . . . . . . . . . . . .Appendix A: AutoCAD Schematic
8 . . . . . . . . . . . . . . . . Appendix B: Complete Breadboard
================================================================================
.CT Problem Statement
The objective of this project is to, using 74LS series chips (00, 04, 08, 11,
21, 32) and an anode seven-segment display (FND507) deisplay a 16-letter phrase
with varying input switches. Jumper wires, a breadboard, and a "Breadboard
Assistant" will be used to connect these components.t
The phrase I will display is "AUTOCADSCHEMATIC," each letter displayed
corresponding directly to the following cube vertices/switch positions (so
chosen that any two consecutive states only require one switch instead of four
like in 0111->1000):
0000 -> 0001 -> 0011 -> 0010 -> 0110 -> 0111 -> 0101 -> 0100 -> 1100 -> 1101
-> 1111 -> 1110 -> 1010 -> 1011 -> 1001 -> 1000.
The breadboard will use the following wire colors convention:
- GND = BROWN
- PWR = WHITE
- W = BROWN
- !W = WHITE
- X = BLACK
- !X = YELLOW
- Y = GREEN
- !Y = RED
- Z = GRAY
- !Z = BLUE
- AND = ORANGE
- OR = PURPLE
- NOT = RED
The Seven-Segment Display will use the following light naming convention:
_______
| a |
| |b
|f |
|_______|
| g |
|e |c
| |
|_______|
d
================================================================================
.CT Truth Table
W X Y Z | VAL | A B C D E F G (1=OFF, 0=ON)
========+=====+==============
0 0 0 0 | A | 0 0 0 1 0 0 0
0 0 0 1 | U | 1 0 0 0 0 0 1
0 0 1 1 | T | 1 1 1 0 0 0 0
0 0 1 0 | O | 0 0 0 0 0 0 1
0 1 1 0 | C | 0 1 1 0 0 0 1
0 1 1 1 | A | 0 0 0 1 0 0 0
0 1 0 1 | D | 1 0 0 0 0 1 0
0 1 0 0 | S | 0 1 0 0 1 0 0
1 1 0 0 | C | 0 1 1 0 0 0 0
1 1 0 1 | H | 1 1 0 1 0 0 0
1 1 1 1 | E | 0 1 1 0 0 0 0
1 1 1 0 | M | 0 1 0 1 0 1 1
1 0 1 0 | A | 0 0 0 1 0 0 0
1 0 1 1 | T | 1 1 1 0 0 0 0
1 0 0 1 | I | 1 1 1 1 0 0 1
1 0 0 0 | C | 0 1 1 0 0 0 0
================================================================================
.CT Unsimplified Boolean Expressions
___ __ _ _ _ _ __
A = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
__ _ _ _ __ __ _ _ _ __ ___
B = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
__ _ _ __ _ __ ___
C = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
____ _ _ _ _ _ __
D = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
_ __
E = WXYZ
_ _ _
F = WXYZ + WXYZ
___ __ _ _ _ _ __
G = WXYZ + WXYZ + WXYZ + WXYZ + WXYZ
================================================================================
.CT Berkeley's ABC!
.CT ---------------
I used Berkeley's ABC: github.com/berkeley-abc/abc.
.CT Genlib File
GATE inv 2.3 O=!a; PIN * INV 1 999 0.9 0.3 0.9 0.3
GATE nand 3.5 O=!(a*b); PIN * INV 1 999 0.9 0.3 0.9 0.3
GATE and2 3.5 O=a*b; PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE and3 4.7 O=a*b*c; PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE and4 7 O=a*b*c*d; PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE or 3.5 O=a+b; PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE buf 1 O=a; PIN * NONINV 1 999 0.9 0.3 0.9 0.3
GATE zero 0 O=CONST0;
GATE one 0 O=CONST1;
.CT PLA file
.i 4
.o 7
.ilb w x y z
.ob a b c d e f g
0000 0001000
0001 1000001
0011 1110000
0010 0000001
0110 0110001
0111 0001000
0101 1000010
0100 0100100
1100 0110000
1101 1101000
1111 0110000
1110 0101011
1010 0001000
1011 1110000
1001 1111001
1000 0110000
.e
On a Bourne shell with abc binary built in current dir:
$ ./abc -c "read circ.pla; read_library gathing.genlib; strash;\
collapse; strash; rewrite; strash; dc2; map; choice; map; print_gates;\
write struct.eqn;"
$ sed -e 's/new_n//g' -e 's/_//g' struct.eqn > struct.eqn.tmp
$ mv struct.eqn{.tmp,} #with some custom cleanup (NAND, moving !x...)
.CT Network Structure from Berkeley's ABC
a = NAND(y,x) * z;
16 = !w * !y;
17 = x * !w;
18 = 17 + 16;
20 = !z * y;
21 = 20 + 18;
23 = z + !x;
b = NAND(23,21);
25 = !16;
26 = z + !y;
27 = 26 + 17;
28 = y * w;
29 = NAND(z,x);
30 = 29 + 28;
c = 25 * 30 * 27;
32 = z * !y;
33 = 32 + 20;
34 = 33 * w;
35 = !z + y;
36 = 18 * 35 * 23;
d = 36 + 34;
38 = !z * x;
e = 38 * 16;
40 = 28 * 38;
41 = 32 * 17;
f = 41 + 40;
43 = !x * w;
44 = 43 + 26;
45 = 35 + x;
g = NAND(45,44);
Total cost:
- 12 2AND = 3 74LS08
- 4 NAND = 1 74LS00
- 5 NOT = 1 74LS04
- 2 3AND = 1 74LS11
- 12 OR = 3 74LS32
================================================================================
.CT Breadboard Schema
The positions are labeled as follows: each board has a code "1." or "2.", a set
of rows 1-80, and columns A-E,F-J. The following describe wires on a real
breadboard. Power/GND rails are implied because they aren't complex. All chips
are at "left is low" and for 7-seg, A-E=A-E side.
74LS00 @ 2.20-26 (NAND)
74LS04 @ 1.30-36 (NOT)
74LS08 @ 1.10-16, 1.20-26, 3.10-16 (2AND)
74LS11 @ 2.10-16 (3AND)
74LS32 @ 2.30-36, 3.20-26, 3.30-36 (OR)
FND507 @ 2.55-2.59 (7-seg)
0.15J = 1.30A (w)
0.16J = 1.32A (x)
0.17J = 1.34A (y)
0.18J = 1.31G (z)
1.32C = 2.20A (x)
1.34C = 2.21A (y)
2.22C = 1.11I (!x+!y)
1.31G = 1.12G (z)
1.13G = 2.58H ( a=z*(!x+!y) )
1.31A = 1.10D (!w)
1.33A = 1.11A (!y)
0.16I = 1.13A (x)
1.10A = 1.14A (!w)
1.12A = 2.30A (!w * !y) #16
1.15A = 2.31A (!w * x) #17
2.32A = 2.33D (!w!y + !wx) #18
================================================================================
.CT Difficulties
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